1. Field of the Invention
The present invention relates, generally, to digital timing schemes, and more particularly, to the selection of a set of clock signals from among a plurality of input clock signals.
2. Description of the Related Art
A wide array of applications involving serial communication between devices (e.g., chip-to-chip, peripheral I/O, and processor-to-processor communication) employ a clock-and-data recovery (CDR) circuit to recover a clock signal from a received asynchronous data signal, and the recovered clock signal is then used to sample the received data signal. A typical CDR circuit recovers a clock signal, e.g., using a phase-locked loop (PLL) to lock the phase of a reference clock signal to the phase of the received data signal. A CDR circuit typically selects the reference clock signal by comparing the phase of the received data signal with the phases of a set of candidate clock signals, which may represent, e.g., time-shifted or interleaved phases of a single clock signal. After determining the reference clock signal, the CDR circuit re-times the received data based on the reference clock signal.
FIG. 1 illustrates an exemplary plurality of time-shifted input clock signals C[0:31] from which a set of candidate clock signals might be selected, wherein consecutive input clock signals are uniformly time-shifted relative to one another. The selected set of candidate clock signals generally comprises clock signals that are consecutive. For example, a selection of 8 consecutive input clock signals from among input clock signals C[0:31] starting with input clock signal C[10] results in the set of candidate clock signals C[10:17]. The word “consecutive,” as used herein, includes the case in which two or more candidate clock signals are selected from a plurality of input clock signals, wherein the bit reference numerals of the two or more selected candidate clock signals are consecutive integers, e.g., C[0:5] or C[22:23]. It should be noted that candidate clock signals C[0:31] “wrap around” so that input clock signal C[0] is considered to be consecutive with C[31]. That is to say, all of the input clock signals are evenly distributed over 360 degrees, such that not only are consecutive input clock signals uniformly time-shifted relative to one another, but the last input clock signal C[31] and the first input clock signal C[0] are uniformly time-shifted relative to one another, as well. Accordingly, the word “consecutive,” as used herein, should be understood to include the case in which the set of candidate clock signals includes both C[0] and C[31], which are still considered to be consecutive, even though their respective bit reference numerals are not consecutive integers.
FIG. 2 illustrates a prior-art phase selector 220, as might typically be used to select and provide to a CDR circuit a set of consecutive candidate clock signals from among a plurality of input clock signals. As shown, phase selector 220 comprises a controller 250 and a set of 32:1 multiplexers (muxes) 202(0)-202(7). Each mux 202(i) receives all 32 input clock signals and outputs only a single (candidate) clock signal out[i], based on a 5-bit selection signal sel(i)[4:0] generated by controller 250. Controller 250 contains logic for receiving a starting phase number k (e.g., supplied by the CDR circuit) and calculating the values of selection signals Sel(0)[4:0]-Sel(7)[4:0] to be provided concurrently to muxes 202(0)-202(7). Controller 250 sends selection signal Sel(0)[4:0] to mux 202(0), so that mux 202(0) selects input clock signal C[k]. At the same time, controller 250 sends selection signal Sel(1)[4:0] to mux 202(1), so that mux 202(1) selects input clock signal C[k+1]. At the same time, controller 250 sends selection signal Sel(2)[4:0] to mux 202(2), so that mux 202(2) selects input clock signal C[k+2], and so forth.
Disadvantageously, in phase selector 220, all 32 input clock signals C[0:31] are routed to each different 32:1 muxes 202(i), and a different 5-bit control signal Sel(i)[4:0] is routed to each mux 202(i), thereby employing a relatively large physical layout area, consuming much power, and having a large fanout. Fanout refers to the number of outputs that can be driven by a logic circuit.
Moreover, relatively complex logic may need to be provided for handling the “wrap-around” case, since input clock signals C[0:31] are evenly distributed over 360 degrees, so that, e.g., if the set of output clock signals out[0]-out[7] includes both C[31] and C[0], the selection of input clock signals will cause one or more upper muxes to select input clock signals up to and including C[31] and one or more lower muxes to select input clock signals starting from and including C[0].
Furthermore, in many applications, the total number of clock signals to select is significantly larger than in the example of FIG. 2, such as selecting 20 out of 100 input clock signals, which would involve a significantly large layout area and fanout and would consume significant power to route all 100 clock signals to each of 20 different muxes and a different 7-bit control signal to each of the 20 muxes.
The technique of phase selection is also used in a variety of applications other than digital timing recovery, e.g., serial-to-parallel data conversion, and there is a need for a low-power phase selector that permits selection of a set of clock signals embodying consecutive phases from among a number of input clock signals, without requiring significant layout area or fanout.